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_attribute_ram_code_ void rf_drv_private_2m_init()
{
//tbl_rf_init
write_reg8(0x12d2, 0x9b);//DCOC_DBG0
write_reg8(0x12d3, 0x19); //DCOC_DBG1
write_reg8(0x127b, 0x0e); //BYPASS_FILT_1
write_reg8(0x1279, 0x38);
//start add follow setting follow 8278 drv
write_reg8(0x124a, 0x0e); //POW_001_010_L
write_reg8(0x124b, 0x09); //POW_001_010_H
write_reg8(0x124e, 0x09); //POW_101_100_L
write_reg8(0x124f, 0x0f); //POW_101_100_H
write_reg8(0x1254, 0x0e); //POW_001_010_L
write_reg8(0x1255, 0x09); //POW_001_010_H
write_reg8(0x1256, 0x0c); //POW_011_100_L
write_reg8(0x1257, 0x08); //POW_011_100_H
write_reg8(0x1258, 0x09); //POW_101_100_L
write_reg8(0x1259, 0x0f); //POW_101_100_H
write_reg8(0x1276, 0x50); //FREQ_CORR_CFG2_0
write_reg8(0x1277, 0x73); //FREQ_CORR_CFG2_1
//For optimum Rx chain
write_reg8(0x134e, 0x45); //CBPF_TRIM_I && CBPF_TRIM_Q
write_reg8(0x134c, 0x02); //LNA_ITRIM=0x01(default)(change to 0x02[TBD])
//end add
//tbl_rf_private_2m
write_reg8(0x1220, 0x04);//SC_CODE
write_reg8(0x1221, 0x2a);//IF_FREQ
write_reg8(0x1222, 0x43);//HPMC_EXP_DIFF_COUNT_L
write_reg8(0x1223, 0x06);//HPMC_EXP_DIFF_COUNT_H
write_reg8(0x1254, 0x0e); //AGC_THRSHLD1_2M_0
write_reg8(0x1255, 0x09); //AGC_THRSHLD1_2M_1
write_reg8(0x1256, 0x0c); //AGC_THRSHLD2_2M_0
write_reg8(0x1257, 0x08); //AGC_THRSHLD2_2M_1
write_reg8(0x1258, 0x09); //AGC_THRSHLD3_2M_0
write_reg8(0x1259, 0x0f); //AGC_THRSHLD3_2M_1
write_reg8(0x400, 0x1f);//tx mode
write_reg8(0x402, 0x44);//preamble length //////send pre len 4 byte
write_reg8(0x404, 0xea);//nordic head
write_reg8(0x421, 0xa1);//len_0_en
write_reg8(0x430, 0x3c);//<1>hd_timestamp
//AGC table
write_reg8(0x460, 0x36);//grx_0
write_reg8(0x461, 0x46);//grx_1
write_reg8(0x462, 0x51);//grx_2
write_reg8(0x463, 0x61);//grx_3
write_reg8(0x464, 0x6d);//grx_4
write_reg8(0x465, 0x78);//grx_5
////Add start the following settings compared with tbl_rf_zigbee_250k and these settings are default values.
write_reg8(0x122a, 0x90);
write_reg8(0x122c, 0x38);
write_reg8(0x123d, 0x00);
write_reg8(0x420, 0x1e);
write_reg8(0x405, 0x04);
write_reg8(0x422, 0x04);
write_reg8(0x408, 0xc9);
write_reg8(0x409, 0x8a);
write_reg8(0x40a, 0x11);
write_reg8(0x40b, 0xf8);
write_reg8(0x407, 0x01);
write_reg8(0x403, 0x44);
//// add end
write_reg16(0xf06, 0);//rx wait time
write_reg8(0x0f0c, 0x54); //rx settle time: Default 150us, minimum 85us(0x54+1)
write_reg16(0xf0e, 0);//tx wait time
write_reg8(0x0f04, 0x70);//tx settle time: Default 150us, minimum 113us(0x70+1) //////can open short time
write_reg8(0xf10, 0);// wait time on NAK
reg_dma_chn_en |= FLD_DMA_CHN_RF_RX | FLD_DMA_CHN_RF_TX;
//g_RFMode = RF_MODE_PRIVATE_2M;
rf_rx_buffer_set((u8 *)rx_packet, RX_FRAME_SIZE, 0);
//rf_acc_len_set(5);
write_reg8(0x405, (read_reg8(0x405)&0xf8) |5); //access_byte_num[2:0] ////// access code 5 byte
write_reg8(0x420, 38); ////// 40-2 =38 , 2 bit error ÈÝ´í
rf_set_tx_rx_off();
rf_rx_acc_code_enable(0x01);
rf_tx_acc_code_select(0);
irq_disable();
irq_clr_src();
rf_irq_src_allclr();
irq_enable_type(FLD_IRQ_ZB_RT_EN); //enable RF irq
rf_irq_disable(FLD_RF_IRQ_ALL);
rf_irq_enable(FLD_RF_IRQ_TX | FLD_RF_IRQ_RX | FLD_RF_IRQ_RX_TIMEOUT); //
irq_enable();
}这里面发射功率怎么改,改的化,发射功率对应写入的寄存器是多少。找不到芯片手册,不知道寄存器写入范围和怎么计算。
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